The present invention is related to an improved capacitor suitable for use with a high packing density of electrical components and particularly capacitors. More specifically, the present invention is related to an improved external lead design which allows for a high height to width ratio in electronic components and specifically in stacked multi-layered ceramic capacitor (MLCC's).
In designing modern complex electrical circuits there are many considerations beyond the electrical specifications. Component stability during the assembly process is one very important criterion which must be considered in the design. As efforts continue towards further miniaturization this consideration becomes even more important. Increased lateral packing, parallel to the surface of the circuit board, has become increasingly more difficult due to the high demand for additional components. Therefore, taking advantage of vertical space, perpendicular to the surface of the circuit board, has been the subject of much focus. Further exploitation of the vertical direction requires components with a high aspect ratio, or height to shortest width ratio, which creates additional problems.
Components with a high aspect ratio cause problems during assembly since they are prone to shift, or topple over, during the assembly and solder reflow or attachment process. Typically, a component having a height to width aspect ratio of no more than about 1:1 is mechanically stable and not susceptible to toppling. However, as the aspect ratio increases the component becomes more unstable and is more susceptible to toppling.
One approach to solving the problem of toppling is the use of thru-hole technology where components have leads that extend through holes in the substrate or circuit board. The leads provide electrical contact between the component and the circuit board and provide mechanical stability to the component during the assembly and attachment process. Thru-hole technology has been, and is still being, used in the electronics industry typically in larger and more bulky type of electronic applications that utilize larger components with a low density interconnect applications such as less than approximately 50 interconnects per square inch.
For higher density applications, such as greater than about 50 interconnects per square inch, surface mount technology is preferred since this allows greater than 600 interconnects per square inch. The high density capability is achieved by miniaturizing the components and eliminating the leads from the components and by eliminating the respective thru-holes in the circuit board. The component leads are replaced by terminations on the component which are then soldered directly to the solder pads on the surface of the circuit board. Surface mount technology utilizes solder paste that is deposited onto each solder pad. The component is positioned and placed on the solder pads thereby making electrical contact with the circuit trace through the solder paste. Once all of the components are placed onto the circuit board the assembly is then passed through a solder reflow oven to reflow the solder paste thus making the same type of electrical and mechanical connection as does solder wave technology. Surface mount technology allows for a high density of components but the high density requires the use of components with a low aspect ratio to avoid toppling during solder reflow.
Component miniaturization exasperates the conflict between the size of components and their performance capability. Those of skill in the art are faced with the conundrum of using thru-hole technology, and forfeiting lateral packing density, or surface mount technology, which limits component geometry.
This problem is particularly relevant with MLCC's since the capacitance of the device is directly related to the size of the component. In the particular case of MLCC's, as their size decreases their capacitance decreases thereby creating a problem for the designers as they strive to meet electrical design requirements which demand more functionality and performance in a smaller package. One solution is to use a small footprint sized MLCC and stacking the MLCC's on top of one another. The capacitance value is then multiplied by the number of capacitors in the stack thus enabling the designer to meet both the foot print size requirement as well as the capacitance requirements. However, stacking small components on top of another increases the aspect ratio thereby creating a mechanically unstable part that is prone to toppling during assembly. Thru-hole, or mechanical supports, as now practiced in the art, increases the footprint which is contradictory to miniaturization as mentioned above.
There has been a long-standing, and now critically important, desire for a system and components which allow for use of vertical space on a circuit board without losses of lateral space while avoiding assembly issues such as component toppling. The present invention provides a solution to these contradictory desires.